The construction of the 2-Mpixel, >32-frame, 200 ns imaging system is complicated by the tremendous requirements on data recording bandwidth, as well as by equally severe demands on the instantaneous power (ground) that has to be delivered to front-end electronics and sensor during acquisition. The bandwidth demands during processing imply that, for flash radiography, a considerable number of frames might be stored momentarily within the confines of the pixel imaging electronics. This in turn requires the ability to dedicate large amounts of silicon area to every pixel in a dense imager. It is not known whether this requirement can be met by traditional packaging concepts, such as the “camera-on-a-chip” or the traditional (hybrid) focal plane array (FPA). The signal conditioning, and analog storage or digitization and ˜1 kilobits digital storage require, for each pixel, significantly more surface area than is currently available in the footprint of a unit pixel cell.
Normally, a “camera-on-a-chip” is a monolithic integrated circuit (IC) in which the semiconductor elements formed contribute both to detection (conversion of photon energy to electronic charge) and processing (manipulation and extraction of information from charge). These “camera-on-a-chip” devices exploit the considerable sophistication of modern IC fabrication processes to perform many sophisticated processing functions, in theory, but are however limited by the most significant constraint that all processing must fit within the confines of the pitch of a pixel unit cell. In other words, if a unit pixel cell was a 100 micron (μm) square, then all electronic circuits for the pixel-unique processing must co-reside in a 100×10 μm2 area.
It is possible to perform additional processing “away” from the limited area of the unit pixel cell, subject to the significant limitations of interconnections used to access each pixel. The interconnection limitations become quite severe as the number of pixels grows, and the limited availability of physical wire channels force significant compromises in the level of sophistication of processing and the frame rate of imaging operations possible. Ideally, therefore, it would be desirable to confine processing to the unit pixel cell and to employ simpler methods of extracting post-processed information from these unit cells.
If it were possible to amplify, extract, store, and compress the information of many individual frames for each pixel within its own unit cell, then it would be possible, in principle, to sequence the readout of this information from each pixel in a time-multiplexed fashion over a relative small number of wires (proportional in number to the square root of the number of pixels in a square focal plane array). Achieving the increased functionality requires either making the unit cell very large or finding a way to fit more circuitry within the same unit area of a pixel. The first approach is clearly unsatisfactory, as it is generally desired to achieve the most aggressive (i.e., small) unit pixel size possible to improve spatial resolution, while maintaining good light collection efficiency. Hence, the second approach is often considered.
One scheme for increasing the amount of circuitry in a planar projection (i.e., the unit area) is proposed by the current inventors and involves 3-D arrangement of silicon. The stacking of silicon to increase the utilization of surface is not unlike the concept of high-rise buildings and multi-level parking structures, which seek to more effective use an otherwise limited piece of real estate. Of course, any additive processing increases the number of steps needed for construction and in general 3-D approaches are expensive due to their additive processing requirements. The aim of the present inventors is therefore to provide the advantages of 3-D packaging of circuitry close to the pixel, reducing the complexity of interconnections while providing for the greatly expanded potential to devote effective more circuitry to each pixel.